The present invention relates to a signal transmission technology for transmitting a greater quantity of digital signals via a less number of signal lines on the occasion of transmitting the digital signals in a communication device, an information processing device, etc.
A means for transmitting the greater quantity of digital signals via the less number of signal lines has hitherto been, for example, such a signal transmission method that a parallel-serial converter transmits the parallel signals as serial signals, and the serial signals are serial/parallel-converted on a receiving side, thereby acquiring the original parallel signals.
When the originally-parallel signals are simply rearranged as the serial signals and thus transmitted, a problem arises, wherein a bit order thereof is not stored.
FIG. 14 illustrates this problem. In a case where a transmitting side inputs the parallel signals having a bit count n to a parallel-serial converter 91, signals d11, d21 are inputted in time-series to an input DI1. Further, signals d12, d22 are sequentially inputted to an input DI2, and signals d1n, d2n are sequentially inputted to an input DIn. Then, the parallel-serial converter 91 converts these signals into serial signals DS in such sequences as d11, d12, d13, d14 . . . d1n, d21, d22, and transmits these serial signals.
On the other hand, on the receiving side, a serial/parallel converter 92 converts the received serial signals DS into the parallel signals but is unable to recognize a delimiter of a bit order of the data and therefore converts the signals into the parallel signals delimited by n-bits at proper portions. Accordingly, it follows that the parallel signals having a different bit order from the bit order (the delimiter and an arrangement sequence of the data) of the original parallel signals, are to be regenerated. For instance, the example in FIG. 14 is that a certain train of time slot signals d21 through d2n on the input side becomes signals d1n=1 through d2n−2.
Therefore, for example, a data transmission method was proposed, wherein in the case of transmitting digital video signals as the serial signals, the signals are transmitted in a way that adds a train of data for synchronization on a one-line-data-by-one-line-data basis of the video signals, while on the receiving side, the video signals are regenerated based on the synchronization data train (refer to Patent document 1).
In the case of thus adding the synchronization data train to the data train based on the video signals, it follows that a data size of the data to be transmitted increases corresponding to this addition, and hence the data train having the addition of the synchronization data train (which is a composite data train) is processed with a faster clock than a clock for processing the video signals, resulting in a complicated configuration of the device such as generating different clocks by a PLL (Phase Locked Loop) circuit.
Further, in a large capacity transmission method employing a plurality of the serial transmissions, a delay difference occurs between the serial transmissions, and there is a necessity of absorbing this delay difference.
FIG. 15 is an explanatory diagram showing the delay difference between the serial transmissions. If a delay difference (Δdelay) occurs between the serial transmissions when transmitting plural rows of serial signals, this delay difference appears in received data on the receiving side. This delay difference is allowable if small enough to be compared with a transmission speed, however, an allowable time difference decreases as the transmission speed rises, resulting in a problem.
Patent Document 1
Japanese Patent Application Laid-Open Publication No. 2001-103474